library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown is
port( clk50m,rst,key:in std_logic;
dig:out std_logic_vector(4 downto 1);
seg:out std_logic_vector(6 downto 0);
led:out std_logic
);
end countdown;
architecture ach of countdown is
component countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer ;
cout:out std_logic
);
end component;
component freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end component;
component mypll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT std_logic;
locked : OUT STD_LOGIC
);
END component;
component cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end component;
component ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end component;
signal clk1m,clk1k,clk1s,locked:std_logic;
signal qh,ql:integer;
signal qcnt,qshow:integer;
begin
u0:mypll port map(not rst,clk50m,clk1m,locked);
u1:freqn generic map(1000000)
port map(clk1m,locked,clk1s);
u2:freqn generic map(1000)
port map(clk1m,locked,clk1k);
u3:cd port map(clk1s,key,qh,ql);
u4:countn generic map(4)
port map(clk1k,locked,'1',qcnt);
qshow<=qh when qcnt=1 else
ql when qcnt=0 else
10;
dig<="1110"when qcnt=0 else
"1101" when qcnt=1 else
"1111";
u5:ledshow port map(qshow,seg);
led<='0' when qh=0 and ql=0 else
'1';
end ach;
library ieee;
use ieee.std_logic_1164.all;
entity cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end cd;
architecture ach of cd is
begin
process(clk,rst)
begin
if rst='0' then
qh<=6;
ql<=0;
elsif rising_edge(clk) then
if ql=0 then
ql<=9;
if qh=0 then
qh<=0;
ql<=0;
else
qh<=qh-1;
end if;
else
ql<=ql-1;
end if;
end if;
end process;
end ach;
--input number 0~9, and output abcdefg for digital tube
library ieee;
use ieee.std_logic_1164.all;
entity ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end ledShow;
architecture ach of ledShow is
begin
with q select
seg<="1000000" when 0 ,
"1111001" when 1 ,
"0100100"when 2 ,
"0110000"when 3 ,
"0011001"when 4 ,
"0010010"when 5 ,
"0000010"when 6 ,
"1111000"when 7 ,
"0000000"when 8 ,
"0010000" when 9 ,
"1111111" when others;
end ach;
--任意整数分频
library ieee;
use ieee.std_logic_1164.all;
--实体
entity freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end freqN;
--结构体
architecture ach of freqN is
--任意进制计数器元件例化声明
component countN
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
cout:out std_logic;
qdata:out integer
);
end component;
signal qdata:integer:=0;
signal cout:std_logic;
begin
--n进制计数器例化
u0:countN generic map(n)
port map(clk,rst,'1',open,qdata);
--clkout<='1' when qdata--'0';
process(rst,clk)
begin
if rst='0' then
clkout<='0';
elsif rising_edge(clk) then
if qdata=0 then
clkout<='0';
else
clkout<='1';
end if;
end if;
end process;
end ach;
library ieee;
use ieee.std_logic_1164.all;
--实体任意进制计数器
entity countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer;
cout:out std_logic
);
end countN;
--结构体
architecture ach of countN is
--任意进制计数器元件例化声明
signal qtmp:integer:=0;
begin
process(rst,clk) --敏感信号
begin
if rst='0' then
qtmp<=0;
cout<='0';
elsif rising_edge(clk) then
if en='1' then
if qtmp=n-1 then
qtmp<=0;
else
qtmp<=qtmp+1;
end if;
if qtmp=n-2 then
cout<='1';
else
cout<='0';
end if;
end if;
end if;
-- if qtmp=n-1 then
--cout<='1';
-- else
--cout<='0';
-- end;
end process;
qdata<=qtmp;
end ach;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity countdown is
port( clk50m,rst,key:in std_logic;
dig:out std_logic_vector(4 downto 1);
seg:out std_logic_vector(6 downto 0);
led:out std_logic
);
end countdown;
architecture ach of countdown is
component countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer ;
cout:out std_logic
);
end component;
component freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end component;
component mypll IS
PORT
(
areset : IN STD_LOGIC := '0';
inclk0 : IN STD_LOGIC := '0';
c0 : OUT std_logic;
locked : OUT STD_LOGIC
);
END component;
component cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end component;
component ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end component;
signal clk1m,clk1k,clk1s,locked:std_logic;
signal qh,ql:integer;
signal qcnt,qshow:integer;
begin
u0:mypll port map(not rst,clk50m,clk1m,locked);
u1:freqn generic map(1000000)
port map(clk1m,locked,clk1s);
u2:freqn generic map(1000)
port map(clk1m,locked,clk1k);
u3:cd port map(clk1s,key,qh,ql);
u4:countn generic map(4)
port map(clk1k,locked,'1',qcnt);
qshow<=qh when qcnt=1 else
ql when qcnt=0 else
10;
dig<="1110"when qcnt=0 else
"1101" when qcnt=1 else
"1111";
u5:ledshow port map(qshow,seg);
led<='0' when qh=0 and ql=0 else
'1';
end ach;
library ieee;
use ieee.std_logic_1164.all;
entity cd is
port(clk,rst:in std_logic;
qh,ql:buffer integer range 0 to 9
);
end cd;
architecture ach of cd is
begin
process(clk,rst)
begin
if rst='0' then
qh<=6;
ql<=0;
elsif rising_edge(clk) then
if ql=0 then
ql<=9;
if qh=0 then
qh<=0;
ql<=0;
else
qh<=qh-1;
end if;
else
ql<=ql-1;
end if;
end if;
end process;
end ach;
--input number 0~9, and output abcdefg for digital tube
library ieee;
use ieee.std_logic_1164.all;
entity ledShow is
port(
q:in integer;
seg:out std_logic_vector(6 downto 0)
);
end ledShow;
architecture ach of ledShow is
begin
with q select
seg<="1000000" when 0 ,
"1111001" when 1 ,
"0100100"when 2 ,
"0110000"when 3 ,
"0011001"when 4 ,
"0010010"when 5 ,
"0000010"when 6 ,
"1111000"when 7 ,
"0000000"when 8 ,
"0010000" when 9 ,
"1111111" when others;
end ach;
--任意整数分频
library ieee;
use ieee.std_logic_1164.all;
--实体
entity freqN is
generic (
n:integer:=100
);
port(
clk,rst:in std_logic;
clkout:out std_logic
);
end freqN;
--结构体
architecture ach of freqN is
--任意进制计数器元件例化声明
component countN
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
cout:out std_logic;
qdata:out integer
);
end component;
signal qdata:integer:=0;
signal cout:std_logic;
begin
--n进制计数器例化
u0:countN generic map(n)
port map(clk,rst,'1',open,qdata);
--clkout<='1' when qdata
process(rst,clk)
begin
if rst='0' then
clkout<='0';
elsif rising_edge(clk) then
if qdata=0 then
clkout<='0';
else
clkout<='1';
end if;
end if;
end process;
end ach;
library ieee;
use ieee.std_logic_1164.all;
--实体任意进制计数器
entity countN is
generic(
n:integer:=100
);
port(
clk,rst,en:in std_logic;
qdata:out integer;
cout:out std_logic
);
end countN;
--结构体
architecture ach of countN is
--任意进制计数器元件例化声明
signal qtmp:integer:=0;
begin
process(rst,clk) --敏感信号
begin
if rst='0' then
qtmp<=0;
cout<='0';
elsif rising_edge(clk) then
if en='1' then
if qtmp=n-1 then
qtmp<=0;
else
qtmp<=qtmp+1;
end if;
if qtmp=n-2 then
cout<='1';
else
cout<='0';
end if;
end if;
end if;
-- if qtmp=n-1 then
--cout<='1';
-- else
--cout<='0';
-- end;
end process;
qdata<=qtmp;
end ach;
#乔治娜[超话]#C罗妈妈对晨间新闻不断造谣儿子C罗儿媳乔治娜及整个家族
决定发律师函
doloresaveiroofficial声明
我想代表我自己和我的家人(Aveiro家庭)交流
其中包括我儿子@cristiano的妻子@georginagio，我儿子
Hugo的妻子Rubina，我的女婿Alexandre,
@katiaaveirovenicial的丈夫，即我的4个孩子我和11个孙子声明
今天，2023年5月16日，我呼吁我的律师为我的家庭和他们在我生命中所代表的一切洗清我的好名声。
一家著名报纸刊登了一则新闻
portugues(报纸，因此使用和滥用我的家庭的名字来宣传自己)not i cia essa，假诽谤和at e e macabra，它谈到了可怕的行为，我可能会
为了夺走我一个孩子的幸福，这个calunia是假的
毫无根据的...
我的好名声永远不会被扔在大街上
公共，我永远不会允许一个来源
反专业信息请使用我的名字。我将到最后的结果，不仅是为了保护我自己和我的人民，但我也将证明来源，文字和文字，到目前为止说，
他们完全是恶意的，毫无根据的。喜欢……能跟踪我和尊重我的人n的只有我和我要特别注意,如果说话和写作,有什么罪过,免费航班,这种不健康的伤害,会伤害我们
当涉及到我们最宝贵的资产——家庭时，他们不再束缚我。
我的孙辈们，有些人，已经在倾听人民和批评。
正因为如此，我不会放弃，除非这份报纸能证明今天所写的一切。
谢谢你。
阿威罗家庭
决定发律师函
doloresaveiroofficial声明
我想代表我自己和我的家人(Aveiro家庭)交流
其中包括我儿子@cristiano的妻子@georginagio，我儿子
Hugo的妻子Rubina，我的女婿Alexandre,
@katiaaveirovenicial的丈夫，即我的4个孩子我和11个孙子声明
今天，2023年5月16日，我呼吁我的律师为我的家庭和他们在我生命中所代表的一切洗清我的好名声。
一家著名报纸刊登了一则新闻
portugues(报纸，因此使用和滥用我的家庭的名字来宣传自己)not i cia essa，假诽谤和at e e macabra，它谈到了可怕的行为，我可能会
为了夺走我一个孩子的幸福，这个calunia是假的
毫无根据的...
我的好名声永远不会被扔在大街上
公共，我永远不会允许一个来源
反专业信息请使用我的名字。我将到最后的结果，不仅是为了保护我自己和我的人民，但我也将证明来源，文字和文字，到目前为止说，
他们完全是恶意的，毫无根据的。喜欢……能跟踪我和尊重我的人n的只有我和我要特别注意,如果说话和写作,有什么罪过,免费航班,这种不健康的伤害,会伤害我们
当涉及到我们最宝贵的资产——家庭时，他们不再束缚我。
我的孙辈们，有些人，已经在倾听人民和批评。
正因为如此，我不会放弃，除非这份报纸能证明今天所写的一切。
谢谢你。
阿威罗家庭
【小瑶9分雅思口语• Part I• 高分范例】
亲手烹制•请勿转载
Part I：Is punctuality important?
（守时重要嘛？）
Yes, super! I think we should be punctual in any given situation. For example, for job interviews. If you were able to arrive on time, you could make a good impression. By being punctual, you are letting employer know that you are reliable and not tardy. When meeting up with a friend, we often set an appointed time. It’s best if we can honor that time, because that shows that we respect the person we are meeting up with. Personally, I think being late once is OK, but being late on a regular basis only means disrespect.
▲in any given situation 在任何情况下
▲make a good impression 留下好印象
▲reliable adj. 可靠的；靠谱的
▲tardy adj. 磨磨蹭蹭的，迟到的
▲an appointed time 约定时间
▲be on time 按时到达
▲the rush hours 高峰时间段
▲a regular basis 经常
▲disrespect n. 不尊敬
#小瑶每日真题演示##雅思# #决战雅思#
亲手烹制•请勿转载
Part I：Is punctuality important?
（守时重要嘛？）
Yes, super! I think we should be punctual in any given situation. For example, for job interviews. If you were able to arrive on time, you could make a good impression. By being punctual, you are letting employer know that you are reliable and not tardy. When meeting up with a friend, we often set an appointed time. It’s best if we can honor that time, because that shows that we respect the person we are meeting up with. Personally, I think being late once is OK, but being late on a regular basis only means disrespect.
▲in any given situation 在任何情况下
▲make a good impression 留下好印象
▲reliable adj. 可靠的；靠谱的
▲tardy adj. 磨磨蹭蹭的，迟到的
▲an appointed time 约定时间
▲be on time 按时到达
▲the rush hours 高峰时间段
▲a regular basis 经常
▲disrespect n. 不尊敬
#小瑶每日真题演示##雅思# #决战雅思#
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